A typical disk drive includes a spindle motor for rotating a data disk, and an actuator for moving a head carrier that supports read/write heads radially across the disk to access data stored on concentric data tracks on the disk. A spindle motor can be a brush less DC motor having multiple phase windings arranged as a stator, and a rotor having a permanent magnet for rotating the disk. During an acceleration phase, the motor is commutated to start from standstill and accelerate to its operational speed. Thereafter, the motor is commutated to maintain that operational speed, by sequentially energizing appropriate phase windings based on the location of the rotor relative to the phase windings. The energized windings generate torque inducing magnetic fields relative to the rotor magnet that rotate the rotor.
In order to ensure that proper phase windings are energized, indirect or sensorless position detection systems, such as back electromotive force ("back emf") detectors, are utilized to determine the rotor position relative to the windings. Back emf detectors sense back emf transitions in the phase windings, due to magnetic flux caused by a moving rotor, to identify the proper phase windings to be energized. Specifically, when the rotor is moving, the change in the course and direction of the magnetic field lines emanating from the rotor magnet causes a magnetic flux through the stator windings, inducing a current in the stator windings. The current induced in the stator windings is a function of the rotor speed or the frequency of magnetic transitions in the stator windings due to the magnetic flux through the stator windings. The induced current develops back emf voltages across resistors electrically connected in series with the phase windings, wherein the back emf voltages provide rotor position information. Once the rotor position is determined, the motor is commutated by sequentially energizing appropriate windings to provide maximum torque to the rotor.
The timing of the commutations is synchronized with back emf transitions in a phase lock loop ("PLL") controller. A conventional PLL controller typically comprises a multiplexer switch, a phase detector, a filter capacitor and a voltage control oscillator ("VCO") for generating commutation timing signals. The multiplexer switch, coupled to the phase detector, sequences back emf voltages from the windings such that only voltages from windings in the unrecognized ("off") state are processed by the phase detector. The phase detector converts the voltages to signals or currents to charge or discharge the filter capacitor depending on whether the voltages are above or below a motor center tap. In effect, the voltages are integrated relative to the center tap. The VCO then generates an output signal at a frequency proportional to the voltage across the filter capacitor. The output signal is used as a clock signal for timing the commutations, whereby the PLL controller keeps the commutation frequency in phase with the electrical cycles of the motor.
A disadvantage of conventional PLL controllers, however, is that they can lock onto a harmonic of the motor frequency rather than the actual motor frequency. For example, a conventional PLL controller can mistakenly lock on to a harmonic of the motor frequency such that the PLL controller produces commutation timing for a harmonic frequency twice that of the actual motor frequency. As a result, although the commutation and motor frequencies are in phase, the frequency of the commutations does not match the frequency of the electrical cycles of the motor.
To solve this problem some PLL controllers further include a frequency detector to detect the frequency of the motor in coast mode and generate a signal causing the VCO to vary the commutation frequency, until the commutation and motor frequencies match. The frequency detector is electrically connected to the motor coils to detect the start of an electrical cycle of the motor, and to the VCO to detect the start of a commutation cycle. Upon detecting the start of an electrical cycle, the frequency detector signal causes the charge pump to charge the filter capacitor and the VCO increases the commutation frequency in response. And upon detecting the start of a commutation cycle, the frequency detector signals the charge pump to discharge the capacitor and the VCO decreases the commutation frequency in response. This process continues until an electrical cycle of the motor and a corresponding commutation cycle occur at the same time.
The frequency detector depends on using the time difference between the start of an electrical cycle and the start of a commutation cycle as the phase error therebetween. The time difference creates a voltage difference at the charge pump causing an incremental change in the frequency of VCO output signal to move the start of a commutation cycle closer to the start of an electrical cycle. By subsequent charge and discharges of the filter capacitor the phase error between the motor frequency and commutations are reduced to a small error. The frequency detector then hands over commutation to the phase detector to keep the commutation frequency in phase with the motor frequency. As such, the PLL controller can generate commutation timing in phase with, and at the same frequency as, the motor.
However, a major disadvantage of PLL controllers with conventional frequency detectors is the inability of such detectors to diminish the phase error between the commutation and motor frequencies for a full range of motor frequencies in minimum time. A mathematical model of the phase error in such controllers can be represented by the following equation wherein the resulting phase error is calculated for (n+1) number of electrical cycles: ##EQU1##
Wherein, K1 is the rate at which the VCO output frequency changes with the VCO input voltage (VCO Gain), K2 is the voltage change at the filter capacitor during the time of charging (Charge Gain), .DELTA.t(i) is the phase error at the ith cycle, V is the starting voltage of the charge pump, and Tt is the period of an electrical cycle of the motor. As such, the rate of reduction in the phase error is controlled by the VCO Gain K1 and by the Charge Gain K2. For each set of K1 and K2 values the phase error can be reduced to a very small error for only a limited motor frequency range. This is because, conventional frequency detectors depend on using the time interval between the beginning of an electrical cycle and the beginning of a commutation cycle as a measure of phase error. Therefore, the frequency detector can overshoot in minimizing the time difference, and the phase error will oscillate in one direction rather than to the other, for a certain range of frequencies.
This shortcoming is evident from numerical solutions to the above equation for high and low motor frequency ranges. In each case below, the phase error is 10% of an electrical cycle. For parameter values of K1=100 Hz/V, K2=0.1/sec, Tt=1 msec, and .DELTA.t(0)=0.1 msec, the phase error is reduced from 0.1 msec to about 5 .mu.sec in about 20 electrical cycles lasting 20 msec. As such, for a high motor speed of about 7200 revolutions per minute ("rpm") in an 8 pole spindle motor, the phase error is reduced to a small value in a bout 20 msec. However, for parameter values of K1=100 Hz/V, K2=0.1/sec, Tt=5 msec, and .DELTA.t(0)=0.5 msec, the phase error is reduced from 0.5 msec to about 100 .mu.sec in about 90 electrical cycles lasting 450 msec, and continues to oscillate at that value thereafter for several hundred msec. As such, the phase error settles to a small value relatively quickly for high motor speeds ranging from about 4200 rpm to about 7000 rpm, but fluctuates greatly for an extended period of time for low motor speeds ranging from about 100 rpm to about 4200 rpm.
A major disadvantage of such a shortcoming is that a conventional PLL controller cannot be reliably used to "hot start" a spindle motor after loss of power. When there is a power interruption, the motor enters a "coast" mode wherein the inertial momentum of the rotor keeps the rotor spinning until friction or breaking bring the rotor to a stop. The motor speed can range from 300 rpm to 7200 rpm depending on the length of the power interruption. Due to the power loss the phase detector in the PLL controller loses track of the motor frequency and must rely on the frequency detector to detect the proper motor frequency before the phase detector can take over and commutate the motor back to its operational speed. In many applications it is crucial to "hot start" the motor after power is restored by commutating the motor back to its operational speed as quickly as possible. However, due to the limited dynamic range of conventional frequency detectors, existing PLL controllers cannot commutate the motor back to its operational speed in minimum time for the full range of frequencies which a motor can experience. As such, either the motor must be brought to a complete stop and restarted again or an entire processing system must idle while the PLL controller attempts to commutate the motor properly.
There is, therefore, a need for a frequency detector for a PLL controller capable of reliably detecting motor frequencies for a full range of motor speeds in minimum time.